TAIPEI (Taiwan News) — Global Unichip Corporation announced Thursday the first universal chiplet interconnect express physical layer chip made with TSMC’s N3P (3nm) process.

GUC explained in a press release that the chip uses a Chip on Wafer on Substrate (CoWoS) design, which is when chips are stacked onto a thin silicon layer. It added that its second-generation universal chiplet interconnect express physical (UCIe) delivers an impressive bandwidth density of 10 Tbps per 1 mm of die edge (5 Tbps/mm full-duplex), per CNA.

To ensure seamless integration, the chip designer developed optimized bridges featuring low power consumption, minimal data latency, and efficient end-to-end flow control.

GUC added that its UCIe features preventive monitoring and integrated I/O signal quality monitors from proteanTecs for reliability. The technology allows for signal integrity monitoring and can catch defects or bumps early, allowing for repair algorithms to kick in.

“We are committed to delivering the highest performance and lowest power 2.5D/3D chiplet and HBM interface IPs,” GUC CTO Igor Elkanovich said. He added that 2.5D and 3D packaging technologies allow for modular processors that exceed reticle size limitations.

The new chip will be used in AI, high-performance computing, and networking. Additionally, the company is developing a third-generation UCIe, which will achieve speeds of up to 64 Gbps per channel and will be finalized in the second half of this year.