TAIPEI (Taiwan News) — AMD announced Monday its next-gen Epyc processor has completed tape-out.

Codenamed “Venice,” the chip was built on TSMC’s advanced 2 nm process, per CNA. Generally, the smaller the process, the more powerful the chip.

AMD said in a press release that Venice represents the successful integration of next-gen architecture with TSMC’s most advanced node. The chip remains on track for commercial launch next year, in line with AMD’s data center roadmap.

AMD CEO Lisa Su (蘇姿丰) praised TSMC as a longstanding strategic partner. She said AMD is the first high-performance computing (HPC) customer for TSMC’s 2 nm process and its Arizona Fab 21.

TSMC Chair and CEO C.C. Wei (魏哲家) said the collaboration with AMD is driving breakthroughs in performance and power efficiency.

“We are proud to have AMD be a lead HPC customer for our advanced 2 nm process technology and TSMC Arizona fab,” he said. “We look forward to continuing to work closely with AMD to enable the next era of computing.”